cache line locking on AMD x86_64 utilising L3 CAT pseudo-locking
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- Makefile 2.6%
| bindings/ocaml | ||
| include | ||
| src | ||
| tools | ||
| Makefile | ||
| README.md | ||
icepick
kernel module for l3 cache pseudo-locking via cat and wc-mapped i/o space.
overview
icepick exposes a character device for pinning data into isolated l3 cache ways. maps physical i/o space with write-combining via ioremap_wc and mtrr configuration, then primes cache lines using prefetcht2 and temporal loads. cat schemata configured through resctrl sysfs. pmu-based eviction monitoring via perf_event (amd zen l3 miss counter 0x0104e). useful for side-channel isolation or latency-critical data structures requiring deterministic cache residency.
requires cat-capable silicon (amd zen2+), resctrl mounted, and kernel headers for kbuild.
build
make
outputs icepick.ko kernel module.
usage
insmod icepick.ko
chmod 666 /dev/cachemem
echo "sensitive data" > /dev/cachemem # lock into l3 way 0
cat /dev/cachemem # read back, integrity check
dmesg | grep ICEPICK # check residency/eviction logs
rmmod icepick
ioctl flush:
#define ICEPICK_IOC_MAGIC 'k'
#define ICEPICK_FLUSH_CACHE _IOW(ICEPICK_IOC_MAGIC, 1, char *)
ioctl(fd, ICEPICK_FLUSH_CACHE, "please flush my cachelines");